基于FPGA的自动变模全数字锁相环的设计

The Design of Automatic Modulus All Digital Phase-Locked Loop Based on FPGA

为了缩短全数字锁相环的捕捉时间,减少同步误差,本文提出了采用双D边沿鉴相器和自动变模控制器相结合的方法,并通过基于Quartus Ⅱ和ModelsimSE的软件仿真对该全数字锁相环的性能进行了验证.仿真结果表明,当进入锁相区时,锁相环趋于动态稳定,只在较小的相位差之间来回摆动,该设计可有效地克服环路捕捉时间与抗噪声性能的矛盾.

In order to shorten the capture time and reduce the synchronization error of all-digital phase-locked loop(PLL);a method combining double D-edge phase discriminator and automatic variable mode controller is proposed in this paper. The performance of the PLL is verified by software simulation based on Quartus II and ModelsimSE. The simulation results show that the PLL tends to be dynamically stable when it enters the PLL region;and only swings back and forth between smaller phase differences. This design can effectively overcome the contradiction between the capture time of the loop and the anti-noise performance.