高速CMOS电路的单元延时模型分析

Analysis of Gate-Delay Models for High-Speed CMOS Circuits

由于互连线电阻引起的时序问题对IC设计带来了越来越大的影响,选取精确的模型来计算延时变得非常重要。本文结合传统延时模型的特点,对有效电流源模型(ECSM)作了改进,通过分段线性方法精确地匹配了负载激励点波形的非线性特性,有效地解决了原模型中存在的不足。经理论分析和实验验证,该模型能快速有效地求解延时,能很好地应用于超深亚微米工艺下的时序分析。

With the narrower IC characteristic size, interconnect resistance plays a greater role in timing. New effective delay models that care about wire resistance are very much needed. After analyzing the traditional timing models, a modified ECSM (Effective Current Source Model), which captures the non-linearity of quasi-capacitive loading by two piecewise-linear approximations, is proposed. Modeling quality is evaluated both by theoretic and experimental approaches, the results show that the improved model possesses advantages in terms of accuracy, speed and adaptability to advanced IC technology.