流水线结构的维特比回溯算法及其实现

A Pipelined Memory Management in Traceback Viterbi Decoders and Its Implementation

维特比解码中,在长约束长度或较深译码深度的情况下,内存管理回溯算法相对寄存器交换法有很大的优势。该文在一种现有的节省内存的内存管理算法的基础上,提出了新的流水线结构的内存管理回溯算法,可以自动处理连续输入的不同长度的帧。并且依据IEEE802.16的高速应用实例,在Xilinx的FPGA上实现了该算法。

The traceback method is one of two known ways to store decisions made by the add-compare-select unit of a Viterbi decode, and then provides decoded bits as output. Memory management traceback method can offer high performance. This paper gives a pipelined memory management method based on a given memory management method, and gives a FPGA implementation for IEEE 802.16 application.