期刊文献+

减少多种子内建自测试方法硬件开销的有效途径 被引量:10

Effective Measures to Reduce Hardware Overhead on Multiseeding BIST
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摘要 提出一个基于重复播种的新颖的BIST方案 ,该方案使用侦测随机向量难测故障的测试向量作为种子 ,并利用种子产生过程中剩余的随意位进行存储压缩 ;通过最小化种子的测试序列以减少测试施加时间 实验表明 ,该方案需要外加硬件少 ,测试施加时间较短 ,故障覆盖率高 ,近似等于所依赖的ATPG工具的故障覆盖率 在扼要回顾常见的确定性BIST方案的基础上 ,着重介绍了文中的压缩存储硬件的方法。 This paper presents a novel build in self test (BIST) approach by reseeding an LFSR It adopts test patterns used to detect random pattern resistant faults as its seeds Don't care bits in those seeds, which are remained during the process of test pattern generation by an automatic test pattern generator (ATPG) tool, are utilized to reduce the size of storage of a seed array Experimental results show that the proposed approach is able to achieve higher fault coverage, which is approximately equal to the one of an ATPG on which the approach depends, and needs less additional hardware overhead for synthesis, and consumes less time for test pattern application After a brief review of those typical deterministic BIST schemes, this paper mainly introduces its scheme of storage compression, synthesis methodology, and experimental results
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2003年第6期662-666,672,共6页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金 ( 60 173 0 42 )资助
关键词 存储压缩 故障覆盖率 寄存器 集成电路 电路测试 多种子内建自测试 linear feedback shift register seed random pattern resistant fault don't care bit
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参考文献7

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同被引文献64

  • 1谢永乐,孙秀斌,王玉文,胡兵,陈光.数字集成电路的混合模式内建自测试方法[J].仪器仪表学报,2006,27(4):367-370. 被引量:13
  • 2张建胜,黄维康,唐璞山.变长重复播种测试码生成方法[J].复旦学报(自然科学版),2006,45(4):517-522. 被引量:5
  • 3师晓卉,秦水介.嵌入式Flash存储器控制器的设计方法[J].电子测量技术,2006,29(5):5-7. 被引量:6
  • 4张建强,冯建华,冯建科.基于自动测试系统的ADC测试开发[J].仪器仪表学报,2007,28(2):279-283. 被引量:16
  • 5雷绍冲.VLSI测试方法学和可测性设计[M].北京:电子工业出版社,2005.
  • 6Yamani S, Mitra S, McCluskey E J. BIST reseeding with very few seeds[A]. 21st IEEE VLSI Test Symposium[C]. 2003,2A(4):69 - 74.
  • 7Ahmed N, et al. Low Power Pattern Generation for BIST Architecture [A]. Proc. of IEEE VLSI Test Symposium[C]. 2001. 329-334.
  • 8Chen C A, Gupta S K. A methodology to design efficient BIST test pattern generators[A]. Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test[C]. Washington, DC, 1995.814 -823.
  • 9[3]Giani A. Novel spectral methods for built-in self-test in a systemon-a-chip environment, VLSI Test Symposium, 19th,IEEE Proceedings on. VTS 2001, 2001 : 163-168
  • 10[4]Zeng Gang. Efficient test data decompression for system-on-a-chip using an embedded FPGA core. Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems . 2003 ;5 :503-508

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