基于FPGA的高频时钟的分频和分配设计

The Design of High Frequency Clock Division and Fan-out with FPG A

介绍了为PET(正电子发射断层扫描仪 )的前端电子学模块提供时间基准而设计的一种新型高频时钟扇出电路。该电路利用FPGA芯片来实现对高频时钟的分频与分配 ,并用LVDS传输标准对生成的多路时钟信号进行传输 ,从而最大程度地减少了输出各路时钟之间的延时偏差 ,同时利用低压差分信号的传输特性增强了信号的抗干扰能力。

A new circuit of fan-out of high frequency clock was designed to provide a reference clock for the frontelectrical mode of PET(Positron emission tomography)systemin this thesis.The circuit performed the diviˉsion and fan-out of high frequency clock by using FPGA,and transformed the clock in LVDS style with the least disturbance as possible.At the same time,it reduced the delay difference between clocks.The program of the clock circuit edited with VHDL language was provided.