摘要
The designing approaches and key fabricating technologies for high frequency high power double dielectrics gate static induction transistor (DDG SIT) with mixed non-saturating I-V characteristics are presented.The effects of parasitic gate-source capacitance (C gs) on the power performance of SIT are discussed.The main methods and considerations to diminish C gs,consequently to improve the high power performance are given.Synchronous epitaxy technology is the critical step to decrease C gs.The 7-μm pitch DDG SIT delivering output power >20W with >7dB power gain and >70% drain efficiency at 400MHz,and delivering output power >7W with >5dB power gain and >50% drain efficiency at 700MHz are successfully fabricated.
提出了用同步外延法设计和制造具有双介质层栅结构和非饱和电流电压特性的高频高功率静电感应晶体管的关键技术 .讨论了寄生栅源电容 Cgs对静电感应晶体管高频功率特性的影响 .描述了工艺上减小寄生电容、改善静电感应晶体管高频功率性能的主要方法和措施 .成功地制造出频率在 4 0 0 MHz时输出功率大于 2 0 W、功率增益大于 7d B、漏效率大于 70 %和 70 0 MHz时输出功率大于 7W、功率增益大于 5 d B,漏效率大于 5 0
