针对MUX-LUT混合结构的FPGA工艺映射算法研究

Technology Mapping Algorithm for FPGA with MUX-LUT Mixed Architecture

针对具有MUX LUT混合结构的FPGA芯片 ,提出一种对其进行工艺映射的面积优化映射算法 该算法的内容包括逻辑门电路到MUX网络的转换方法 ,MUX网络到FPGA芯片逻辑单元的映射方法 文中算法采用模式匹配的方法除去电路中的冗余MUX ,以减少映射结果的面积开销 应用测试电路分别对该算法和Xilinx的Foun dation系统对XC4 0 0 3E芯片的工艺映射结果进行了比较测试 。

An algorithm for doing area-optimal technology mapping for FPGA based on MUX-LUT mixed logic cell structure is presented. The algorithm composes mainly of a conversion from circuit of logic gates to MUX networks and a mapping from MUX networks to logic cells. The algorithm uses pattern-matching method to remove redundant MUX in order to reduce the area cost of the mapping result. We compared our algorithm with that used in Xilinx TM Foundation TM system by a set of benchmark circuits. The comparison result is also presented.