摘要
本文提出了一种系统芯片(SoC)中用于降低内建自测试(Built-in Self-test, BIST)峰值功耗的调度算法。首先本文提出了基于扫描BIST的精简功耗模型,在此模型的基础上,提出了通过调整扫描周期和扫描起动时间的办法来避免过高的SoC测试峰值功耗。实验结果表明,该算法可以有效地避免BIST并行执行可能带来的过高峰值功耗。
A low peak power consumption Built-in self-test (BIST) scheduling algorithm for system-on-a-chip (SoC) is presented. First a compact power model of scan based BIST is proposed. Based on the model, excessive peak power consumption during test can be avoided by adjusting the BIST period and controlling each BISTs startup. Experiment shows that peak power during concurrent BIST execution can be by reduced by the proposed scheduling algorithm.
出处
《电路与系统学报》
CSCD
2004年第1期68-72,共5页
Journal of Circuits and Systems
基金
国家自然科学基金资助项目(60176018)