摘要
基于作者先前提出的时钟馈通补偿方式的开关电流存储单元及全差分总体结构,本文设计了一种二阶开关电流Σ-Δ调制器。工作中采用TSMC 0.35m CMOS数字电路工艺平台,在低电压工作下进行电路参数优化。实验表明,调制器在3.3V工作电压、10MHz采样频率、64倍过采样率下实现10-bit精度。与已有类似研究相比,本工作在相当的精度条件下,实现了低电压、视频速率的工作。
A second-order switched current Σ-Δ modulator is proposed. The modulator is fabricated with full differential architecture consisting of the switched current memory cells based on clock feed-through compensation scheme. The whole modulator is designed and simulated in a 0.35um standard digital CMOS process and optimized for the low-voltage power supply condition. The measurement indicates that the resolution of the modulator reaches 10 bit under the conditions of single 3.3V power supply, 10MHz clock frequency and oversampling ratio of 64. Compared with the other research results, the proposed modulator can be operated with low power supply voltage and high accuracy at video frequency.
出处
《电路与系统学报》
CSCD
2004年第1期111-114,共4页
Journal of Circuits and Systems
