摘要
该文根据现场可编程门阵列 (FPGA)内部结构特点 ,分别从Petri网模型的模块划分和VHDL硬件描述语言的使用两方面 ,讨论了Petri网硬件实现简化的方法和技巧。最后通过具体实例 ,并在max +plusⅡ软件中编译、仿真、综合并适配 ,其结果表明该方法的正确性 ,即使得Petri网硬件电路在FPGA中实现的结构更加优化 ,所占资源率更小。
The paper discussed the techniques and methods for simplifying the implemention of Petri net specification from the aspects of modularizing Petri net specification and using VHDL language according to the internal characteristic of FPGA. Finally,it is verified by an example that is compiled,simulated,synthesized and fitted in max+plusⅡ.The structure of circuit implementing Petri net in FPGA will be optimized and the occupying rate of the device's resource will be lower by these techniques and methods.
出处
《计算机仿真》
CSCD
2004年第1期61-63,共3页
Computer Simulation
