采用独立复位信号的同步时序电路可测试性设计

A Combination of Partial Reset and Observation Point Insertion for Synchronous Sequential Circuits

针对同步时序电路提出一种结合了插入可观测点的部分复位方法 ,该方法是基于迭代计算的电路状态信息和冲突分析测度而提出的 .根据基于电路状态信息的测度和冲突分析所选择出来的部分复位触发器 ,可以割断电路中的关键回路 ,使得电路容易被初始化 ,同时减少在时序ATPG中的潜在冲突 .以前的部分复位方法中 ,部分复位的触发器不能由独立的复位信号所控制 ,这也是不能彻底改善可测试性的一个重要原因 .当部分复位触发器可以由独立的复位信号所控制时 ,电路的可测试性会显著提高 .该文提出了一种新的可测试性结构来设计部分复位触发器 ,该方法同时减小了在管脚。

A partial reset method combined with observation point insertion is presented for synchronous sequential circuits based on a testability measure with respect to iteratively calculated circuit state information and conflict analyseis. Partial reset flip flop selection according to a circuit state information based measure and conflict analysis can break critical cycles of the circuit, make the circuit easy to initialize, and reduce potential conflicts in sequential ATPG. The most important reason why previous partial reset methods cannot completely improve testability is that partial reset flip flops are not controlled by independent reset signals. Testability can be enhanced greatly when partial reset flip flops are judiciously controlled by independent reset lines. A new testability structure is proposed to design a partial reset flip flop, which makes the method economical in pin, delay, and area overheads.