JPEG2000二维离散小波变换高效并行VLSI结构设计

Highly Efficient and Parallel VLSI Architecture Design for JPEG2000 of 2D-Discrete Wavelet Transform

提出一种基于提升算法,实现JPEG2000编码系统中二维离散小波变换(DWT)的高效实时并行VL SI结构设计方法.利用该方法所得结构使行和列滤波器同时进行滤波,用少量行缓存代替大量中间存储空间,用优化的移位加操作替代乘法操作.整个结构采用流水线设计方法处理,在保证同样的精度下,大大减少了运算量,增加了硬件资源利用率,加快了变换速度,减小了电路的规模.二维离散小波滤波器结构已经过VerilogHDL行为级仿真验证,并可作为单独的IP核应用于正在开发的JPEG2000图像编、解码芯片中.

A highly efficient, real time and parallel pipelined architecture that performed the forward and inverse discrete wavelet transform (DWT) was proposed by using a lifting-based scheme for the filters recommended in JPEG2000. The architecture consisted of one row processor and one column processor. And they processed the signals in parallel way via the few line buffers in which the intermediate results were stored. Multiplication was substituted for shift-add operations. The whole architecture was optimized in the pipeline design way to increase the transform speed, and achieve higher hardware utilization. Finally, the architecture had been implemented in behavioral Verilog hardware description language (HDL). The architecture could be used as a compact and independent IP core for JPEG2000 VLSI implementation and various real-time image/video applications.