用于能量回收逻辑的正弦功率时钟电路

A Sinusoidal Power Clock Generation Circuit for Energy Recovery Logic

分析了功率时钟对电容负载充电与回收的物理过程,研究了正弦功率时钟产生电路的基本结构,考虑了功率时钟的频率与相位的稳定性。在此基础上,提出了稳定功率时钟频率与相位的功率时钟产生电路,即接入外部参考时钟,使振荡电路与参考时钟同步。用0.8μmDPDMCMOS工艺实现了一个简化的两相正弦功率时钟产生电路,通过物理测试,验证了电路的工作原理。

The physical process of power clock charging and recovering capacitance load is analyzed,and the basic structure of two-phase sinusoidal power clock generation circuits is studied,while the frequency and phase stability are taken into consideration.Based on the analysis,a frequency and phase stabilized two-phase sinusoidal power clock generator is proposed,which,while connected to an external reference clock, makes the oscillating circuit in synchronization with the reference clock.A simplified version of the power clock generator was realized with 0.8 μm DPDM CMOS process,and a test has been carried out.It has been shown that the proposed circuit functions properly.