一种宽位乘法器设计方案

The Design of Bit-width Multiplier

如何以合理的代价构造尽可能高速的低功耗的乘法器，尤其是位数较宽的乘法器(如32^*32，54^*54和64^*64等)是微处理器数据通路设计中极其重要的环节。文中使用一种折衷的补码分段Booth乘法器。经过论证，最后通过布局布线后的结果看出，补码分段Booth乘法器规模小，速度高，非常适合低功耗嵌入式应用。

When designing data-path of the microprocessor, it is a very important issue about how to design a highspeed and low power multiplier,especially the bit-width is very large (such as 32*32,54*54 and 64*64).This paper presents a 2's complement Booth multiplier using a partition scheme.Also the algorithm has been demonstrated in this paper.Finally, it is shown that this partition scheme is much suitable for low power and embedded application due to its small area and high speed character.