期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

基于改进等分节点法的启发式布局算法 被引量：5

A New Heuristic Algorithm Based on Two Equal Terminals Partition Method for Standard Cell Placement
下载PDF
导出
摘要 针对集成电路标准单元模式的布局问题,提出了一个全新的基于改进等分节点法的启发式标准单元布局算法(TETP).该算法在优化布局过程中采用改进的等分节点法寻找单元目标位置,同时结合局部寻优的启发式算法,对MCNC(MicroelectronicsCentreofNorth-Carolina)标准单元测试电路进行实验.结果表明,与布局工具TimberWolf7.0和FengShui相比,电路布局的总线长度分别平均减少了16%和17%. The new algorithm is applied to find the target location of cell during the placement optimization, and it is combined with a heuristic local optimization approach to experiment on MCNC (Microelectronics Centre of North-Carolina) standard cell benchmarks. The results show that the total wire length is reduced by an average of 16% and 17% in comparison with the placement tools of Timber Wolf7.0 and FengShui, respectively.
作者 程锋 毛军发
机构地区 上海交通大学电子工程系
出处 《上海交通大学学报》 EI CAS CSCD 北大核心 2004年第2期157-160,共4页 Journal of Shanghai Jiaotong University
基金 国家自然科学基金(90207010) 国家高技术研究发展计划(863)项目(2002AA1Z1520) 上海应用材料研究基金项目(0110)
关键词 大规模集成电路 计算机辅助设计 标准单元布局 电路优化 版图 large scale integrated circuits computer aided design standard cell placement circuit optimization layout
分类号 TN402 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献5

  • 1[1]Sun W J, Sechen C. Efficient and effective placement for very large circuits[J]. IEEE Trans Computer-Aided Design, 1995,14(3): 349-359.
  • 2[2]Kleinhans J M, Sigl G, Johannes F M, et al. GORDIAN: VLSI placement by quadratic programming and slicing optimization[J]. IEEE Trans ComputerAided Design, 1991,10(3): 356-365.
  • 3[3]Kernighan B W, Lin S. An efficient heuristic procedure for partitioning graphs[J]. Bell System Technical Journal, 1970, (2): 291-307.
  • 4[5]Yildiz M C, Madden P H. Global objectives for standard cell placement[A]. Proc GLSVLSI[C]. [s. 1. ]:Design Auto Inst, 2001. 68-72.
  • 5[6]Karypis G, Aggarwal R, Kumar V, et al. Multilevel hypergraph partitioning: application in VLSI domain[J]. IEEE Trans on VLSI System, 1999,7 ( 3 ): 69 -79.

同被引文献45

  • 1陆承宇,章文立.CIM电网模型的拓扑分析方法[J].浙江电力,2005,24(4):5-8. 被引量：12
  • 2南国芳,李敏强,寇纪淞.基于适应性模拟退火的标准单元布局算法[J].系统仿真学报,2006,18(3):550-553. 被引量：4
  • 3Srinivasan A, Chaudhary K, Kuh E S. RITUAL:An performance-driven placement algorithm [J].IEEE Trans on Circuits and Systrems-Ⅱ: Analog and Digital Signal Processing, 1992,39 (11):825-840.
  • 4Hamada T, Cheng C K, Chau P M. Prime: a timing-driven placement tool using a piecewise linear resistive network approach[A]. Proc Design Automation Conference[C]. New York: ACM, 1993. 531-536.
  • 5Dunlop A E, Agrawal V D, Deutsch D N, et al.Chip layout optimization using critical path weighting [A]. Proc Design Automation Conference[C]. Piscataway: IEEE, 1984. 133-136.
  • 6Kong T. A novel net weighting algorithm for timingdriven placement[A]. ICCAD[C]. San Jose: IEEE,2002. 172-176.
  • 7Sarrafzadeh M, Knol D A. A delay budgeting algorithm ensuring maximum flexibility in placement[J].IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 1997,16(11):1332-1341.
  • 8Halpin B, Chen C Y, Sehgal N. Timing driven placement using physical net constraints [A]. Proc Design Automation Conference [C]. New York:ACM, 2001. 780-783.
  • 9Cong J, Pan Z G. Interconnect performance estimation models for design planning[J]. IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems, 2001,20(6): 739- 752.
  • 10Parakh P N,Brown R B,Sakallah K A.Congestion driven quadratic placement[A].Proc Design Automatin Conference[C].San Francisco:IEEE,1998:275-278.

引证文献5

二级引证文献29

上海交通大学学报
2004年 第2期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部