65nm技术节点套刻控制的经济价值(英文)

Microeconomics of Overlay Control at the 65 nm Technology Node

国际半导体技术发展路线工作组确定了把套刻控制作为65nm及其以下的技术节点未知解决方法的技术障碍。最严重的问题是总的测量方法不确定、CMP工艺的坚固性以及器件的相互关系。系统的根源引起的图形位置误差(PPE)分析在摩托罗拉公司的DanNoble中心已得到确定,即目前传统的框中框式套刻标记在所有的三种类型引起了缺陷。一种先进的利用成像标记的建议是基于栅格型且能被分割成类似于器件图形的特征图形。在采用193nm光刻设备进行多浅沟道隔离图形套刻的情况下,这种标记显示出将总的测量方法不确定因素减少了40%。

ITRS working groups have identified overlay control as a technology roadblock with no known solutions at the65nm node and beyond.The most serious problems are total measurement uncertainty,CMP process robustness,and device correlation.A systematic root-cause analysis of pattern placement error(PPE)at Motorola's Dan Noble Center has determined that current box-in-box overlay targets cause deficiencies in all three categories.A proposed solution utilizes advanced imaging targets that are grat-ing-based and can be segmented with features that are similar to those in the device.In the case of poly-to-STI overlay using193nm lithography tools,these targets show a40%decrease in total measurement uncertainty.