80MSPS双采样0.34μm硅CMOS开关电容滤波器

An 80MSPS Dual-Rate Sampling 0.34μm Si CMOS Switched-Capacitor Filter

基于双采样和电荷守恒原理 ,并为实现从s到z域准确的双线性变换 ,本文提出了一种新颖的开关电容基本组态 ,进而组构了五阶椭圆低通滤波器 .该滤波器应用典型 0 .34μm/ 3.3V硅CMOS工艺模型进行设计仿真 ,获得了 80MHz采样率、1 7.8MHz截止频率、0 .0 5 2dB最大通带纹波、4 2 .1dB最小阻带衰减和 74mW静态功耗的模拟测试结果 .同时 ,该双采样拓扑结构突破了滤波器受运放单位增益带宽和转换速率的传统约束 ,有效地改善了其高频应用性能 .这一结构已经应用于 1

In the light of principles of dual rate sampling and charge conservation,a novel switched capacitor configuration was proposed in order to realize accurate bilinear transformation from s to z domain,which had been used for building a 5th order elliptic lowpass filter.The filter was simulated and measured in typical 0.34μm/3.3V Si CMOS process models,to achieve 80MHz sampling rate,17.8MHz cutoff frequency,0.052dB maximum passband ripple,42.1dB minimum stopband attenuation and 74mW quiescent power dissipation.The dual rate sampling topology breaks the traditional restrictions of filter introduced by unit gain bandwidth and slew rate of operational amplifiers and also improves effectively their performances in high frequency applications.It has been applied for the design of an anti alias filter in analog front end of video decoder IC with 15MHz signal frequency already.