基于模型参考自适应系统算法的速度估算核的研制

THE IMPLEMENT OF SPEED ESTIMATION CORE BASED ON MRAS ALGORITHM

在集成电路芯片设计中可重复使用核的范围日趋广泛与复杂,在保持各种核的通用性的同时,也越来越要求核的专用性。具有知识产权的核库的建设已成为芯片设计发展的一个重要目标。首先介绍了在无速度传感器控制系统中模型参考自适应的基本原理,最后以CPLD芯片为硬件基础研制了10bit和12bit两种精度的基于MRAS的速度估算核,并进行功能和时序验证,比较了它们所占用的芯片资源的大小。这种速度估算核可以作为一种嵌入式外设和裸MCU或DSP核制成电机控制专用芯片,应用于各种无速度传感器的电机闭环控制系统。

The core in designing IC is growing more complex and abundant, so it requires higher specialization as its availability. Aiming to build up core library, in this paper, the advanced MRAS (Model Reference Adaptive System) scheme based speed sensorless drive of induction motor is presented first. Finally, a common core is created based on CPLD.10-bit system (the result of the estimated speed is a 10-bit digital) and a 12-bit one are presented, morever, their precisions and LC (Logic Cells) usages are compared. Experimental results are given to show its effectiveness. The result shows that designing a high capability AC control IC used this core as an embedded core with other CPU or DSP core can shorten efficiently the CPU processing time and constitute high performance close-loop control system.