快速浮点加法器的全定制设计

Full-custom Implementation of Fast Floating-point Adder

描述了一个流水线运行的、符合IEEE 75 4单精度浮点标准的加法器的全定制设计。该浮点加法器的设计基于SMIC 1 .8V 0 .1 8μm 1p6mCMOS工艺 ,将应用于高性能 32位CPU的浮点运算单元中。该设计在研究快速实现算法结构的基础上 ,采用全定制的电路及版图设计方法 ,提高了浮点加法器的工作速度 ,降低了芯片功耗 ,并通过减少芯片面积 。

The full-custom design of a pipelined floating-point adder conforming to IEEE 754 is presented,which is integrated with a 32-bit high-performance CPU of SMIC 1.8V 0.18um 1p6m CMOS process.Based on the research of the fast algorithm and the full-custom back end implementation,this floating-point adder is expected to achieve high performance,low power dissipation,small chip area,and low cost.