VB高速译码算法及其FPGA实现

High Throughput Viterbi Decoder Algorithm and Its Implementations on FPGA

根据DVB -T标准中FEC内码的要求 ,采用FPGA技术实现了R =1/2 ,6 4状态 ,基 4 ,16电平软判决高速Viterbi译码器。通过将原有基 2蝶形运算分裂为基 4蝶形运算 ,构造出 4路ACS单元。由 4个 4路ACS单元构成的基 4ACS模块一次可以得到 4个状态的两步路径更新 ,使得译码速度提高了 1倍。

According to the request of the internal code FEC in DVB-T standard, a new R=1/2, radix-4, 64-state, 16-level soft-decision Viterbi decoder based on FPGA are presented in this paper. 4-way ACS is constructed through restructuring radix-2 butterfly into a radix-4 butterfly. A radix-4 unit which consists of 4 4-way ACS can obtain two stage surviving path of four states. As a result the throughput becomes twice as before. The FPGA design and optimization for reducing the area and power are also presented.