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一种CMOS折叠结构ADC中的失调抵消技术 被引量：3

A CMOS Folding ADC with Dynamic Element Matching
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摘要 CMOS折叠预放电路的失调是限制 CMOS折叠结构 A/ D转换器实现高分辨率应用的主要原因之一 .文中提出差分对的动态匹配技术改善了折叠预放电路的失调 ,从而为研制 CMOS工艺中的高分辨率折叠结构 A/ D转换器提供了一种可行方案 ,并给出了 MATL AB和电路仿真的实验结果 . The offset of the preamplifier limits the accuracy of a folding ADC.Dynamic element matching technique is proposed to improve the match property of the folding circuit and break through the barrier of high resolution implementation in CMOS technology.The results of MATLAB and circuit simulation are summarized.
作者 李志刚 石寅
机构地区 中国科学院半导体研究所
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2004年第2期206-213,共8页 半导体学报（英文版）
基金 国家高技术研究发展计划资助项目 (编号 :2 0 0 2 AA1Z12 0 0 )~~
关键词 A/D转换器 CMOS模拟集成电路 折叠插值 失调 动态匹配 analog-to-digital converter CMOS analog integrated circuit folding and interpolation offset dynamic element matching
分类号 TN432 [电子电信—微电子学与固体电子学]
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参考文献19

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同被引文献23

  • 1谢应鑫,刘健,毛绍伯.大规模集成电路掩模缺陷激光修正技术[J].激光杂志,1987,8(5):323-326. 被引量：1
  • 2韩书光,池保勇,王志华.A Novel Offset-Cancellation Technique for Low Voltage CMOS Differential Amplifiers[J].Journal of Semiconductors,2006,27(5):778-782. 被引量：3
  • 3Phan A T, Kim C W,Jung M S, et al. A novel 1.5 V DC offset cancellation CMOS down conversion mixer [J]. IEEE International Symposium on Circuits and Systems, 2005, 4:3704-3707.
  • 4Holenstein C, Stonick J T. Adaptive dual-loop algorithm for cancellation of time-varying offsets in direct conversion mixers[C]. IEEE Radio and Wireless Conference, 2000:215-218.
  • 5Phan A T,Kim C W,Jung M S,et al.A novel 1.5V DC off-set cancellation CMOS down conversion mixer. IEEE International Symposium on Circuits and Systems,2005,4:3704
  • 6Holenstein C,Stonick J T. Adaptive dual-loop algorithm for cancellation of time-varying offsets in direct conversion mixers. IEEE Radio and Wireless Conference,2000:215
  • 7Yoshida H,Tsurumi H,Suzuki Y. DC offset canceller in a direct conversion receiver for QPSK signal reception. The Ninth IEEE International Symposium on Personal, Indoor and Mobile Radio Communication, 1998,3 : 1314
  • 8Enz C C,Temes G C. Circuit techniques for reducing the effects of op-amp imperfection, auto-zeroing, correlated double sampling and chopper stabilization. Proceeding of the IEEE, 1996,84(11):1584
  • 9Razavi B. Design of analog CMOS integrated circuits. Boston:McGraw-Hill Higher Education, 2001:463
  • 10Gary P R,Hurst P J,Lewis S H,et al. Analysis and design of analog integrated circuits. New York, John Wiley & Sons,Inc, 1998:231

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Journal of Semiconductors
2004年 第2期

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