一种嵌入式处理器的动态可重构Cache设计

A Dynamic Configurable Cache Design of Embedded Processor

一般的处理器芯片都有片上高速缓存Cache,它一般是由固定大小的一级Cache(L1)和二级Cache(L2)构成,文章介绍了一种在嵌入式处理器设计中实现的动态可重构Cache。动态可重构Cache的思想最早是罗彻斯特大学(UniversityofRochester)的学者在他们的一篇关于存储层次的论文1中提出的,当时主要是针对高性能的超标量通用处理器。在此嵌入式处理器设计过程中,笔者创造性地继承了这一思想。通过增加少量硬件以及编译器的配合,在嵌入式处理器中L1Cache和L2Cache总体大小不变的情况下,L1Cache和L2Cache的大小可以根据具体的应用程序动态配置。通过对高速缓存的动态配置,不仅可以有效地提高Cache的命中率,还能够有效降低处理器的功耗。

Generally the processor has on-chip cache,which is composed of fixed-size top level cache(L1Cache)and second level cache(L2Cache).This paper introduces a dynamically configurable cache structure implemented in the embedded processor design.The idea of dynamically reconfigurable cache originally appeared in a paper about memory-hierarchy,which is written by scholar of University of Rochester 1 .And they aim at high performance superscalar general-purpose processor.During the process we design our embedded processor,we inherit this idea in a creative way.By adding a few hardware and by support of the compiler,the size of L1Cache and L2Cache can be dynamically configured according to application while the total size is fixed in the embedded processor.Dynamically configuration can not only raise the hit rate but also reduce the power dissipation efficiently.