基于CPLD的多通道快速数据栈区设计

Design of Multiple High Speed Data Memory Based on CPLD

利用在系统可编程逻辑器件ispLSI6192芯片构造4个双向并独立的128×9位FIFO高速数据存储栈区(FIFO),并利用芯片内部快速进位逻辑建立快速地址寄存器和地址自动加1计数器,同时利用该芯片的门阵列建立FIFO控制逻辑,控制逻辑分别对4个FIFO栈区进行读写管理控制;即将系统的高速数据栈区及其控制逻辑功能做在同一个芯片上,从而提高计算机数据管理通信的速度、效率,以及提高系统的集成度和降低系统的故障率。

Application ispLSI6192 device make four bi -directional high speed data memory (FIFO) of 128×9 b. We can make address counter and address register base on high -speed adding logic of the device, and make controlling logic base on programmable gate array and programmable register array. Controlling logic manage and control reading or writing operation of FIFO1-4 data memory, and because system's high speed data memory and it's controlling logic are in same device, so we can improve efficiency and speed of computer data managing and communications, and improve system's integer and reduce system's error.