32位MIPS微处理器中乘法器的设计和实现

The Multiplier's Design and Realization in 32-bit MIPS Microprocessor

在Booth算法的基础上 ,结合MIPS 4KC微处理器中的流水线结构和乘法器的工作过程 ,提出了一种改进的Booth乘法器的设计方法 ,并采用全制定方法实现 ,用这种方法实现的乘法器单元具有面积小、单元电路可重复性好、版图设计工作量小、功耗低等特点。

Multiplier is the critical block of processor. This paper gives a new multiplier in MIPS 4KC pipeline CPU based on Booth arithmetic, which is suitable for the full-custom design and could reduce the area, make the circuit and layout design easier and simpler, and also reduce the power consumption.