深亚微米ASIC设计中的时序约束与静态时序分析

Timing Constraints and Static Timing Analysis(STA) Used in Deep Submicron ASIC Design

在现代深亚微米专用集成电路 (ASIC)设计流程中 ,为使电路性能达到设计者的预期目标 ,并满足电路工作环境的要求 ,必须对一个电路设计进行诸如时序、面积、负载等多方面的约束 ,并自始至终使用这些约束条件来驱动电路设计软件的工作。文中介绍了设计中所需考虑的各种时序约束 ,并以同步数字系列 (SDH)传输系统中 8路VC12 VC4E1映射电路设计为例 ,详细说明了设计中所采用的时序约束 ,并通过静态时序分析 (STA)方法使电路时序收敛得到了很好的验证。

In modern deep submicron ASIC design flows, many constraints such as timing, area and load should be set to meet the design goal and the requirements of operation environment. Moreover, all these constraints must be used to drive the EDA tools throughout the design flow .The basic timing constraints concept in ASIC design has been introduced in this paper, then with the ASIC design of VC12-VC4 E1 mapper in SDH system, the related timing constraints have been demonstrated in detail. The timing requirements have been well met with STA tool, PrimeTime (SYNOPSYS).