10Gbit/s0.18μmCMOS光纤通信用数据判决电路设计

Design of 10 Gbit/s Data Decision Circuit for Optical Fiber Communication Using 0.18 μm CMOS Technology

介绍了采用TSMC公司 0 .18μmCMOS工艺设计速率为 10Gbit/s的数据判决电路 ,分析了数据判决电路的系统结构以及单元电路结构 ,给出了仿真结果。该电路采用 + 1.8V电源供电 ,功耗为 10 2mW ,5 0Ω负载上单端输出摆幅 4 0 0mV。整个芯片面积为 0 .80mm× 1.0 5mm。

A 10 Gbit/s data decision integrated circuit(IC) using 0.18 μm CMOS technology is introduced. The system architecture of the circuit and the configuration of the cell block are analyzed, and the simulation results are given at last. Under the supply voltage of +18 V, the power consumption of the total decision IC is 102 mW, the single-ended output signal has constant output voltage swing of 400 mV on 50 Ω load. The chip area is 0.8 mm×1.05 mm.