期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

用遗传算法优化测试通路结构设计 被引量：1

Optimizing Test Access Architecture by Genetic Algorithm
下载PDF
导出
摘要 嵌入核测试通路问题是片上系统设计中的重要问题 由于嵌入核与芯片的输入 /输出管脚没有直接通路 ,因此需要设计专门的测试通路结构对它们进行测试 ,以减少测试时间 ,降低测试成本 提出一种基于遗传算法的优化算法来设计测试通路结构 ,并选取了两个假定的、比较复杂的片上系统作为例子 实验结果表明 ,文中算法搜索到全局最优解 (或近似全局最优解 ) Test access is a main issue encountered in the core based system on chip (SOC) design For an embedded core, which is deeply embedded in the system chip, direct physical access to its peripheries is not available by default; hence, additional access mechanisms are required An approach based on genetic algorithm is proposed to deal with several issues related to the design of optimal test access mechanisms that minimize test time of SOC, including the assignment of cores to test buses, and distribution of test data width between multiple test buses As a case study, the test access mechanisms of two hypothetical but nontrivial systems are optimized by our approach Experiment results show that the proposed algorithm performs better in global optimum searching than the existing method based on integer linear programming (ILP)
作者 王英翔 黄维康
机构地区 复旦大学电子工程系CAT室
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2004年第3期348-354,共7页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金 ( 60 0 73 0 3 2 90 2 0 70 0 2 )资助
关键词 片上系统 遗传算法 优化 测试通路结构 设计 system on chip embedded core test access mechanism genetic algorithm
分类号 TN492 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献14

  • 1郑赟,黄国勇.通过遗传算法进行系统级软硬件划分[J].计算机辅助设计与图形学学报,2002,14(8):731-734. 被引量：12
  • 2Zorian Y, Marinissen E J, Dey S. Testing embedded-core-based system chips [A]. In: Proceedings of the IEEE International Test Conference, Washington D C, 1998. 130- 143.
  • 3Marinissen E J, Zorian Y, Kaput R, et al. Towards a standard for embedded core test: An example [A]. In: Proceeding of the International Test conference, Atlantic City, NJ, 1999.616627.
  • 4Beenker FPM, Bennetts RG, Tijssen AP. Testability Concepts for Digital ICs-the Macro Test Approach [M]. Boston:Kluwer Academic Publishers, 1995.
  • 5Ghosh I, Jha N K, Dey S. A low overhead design for testability and test generation technique for core-based systems [A]. In:proceedings of the IEEE International Test Conference,Washington D C, 1997. 50-59.
  • 6Marinissen E J, Arendsen R, Bos G, et al. A structured and scalable mechanism for test access to embedded reusable cores[A]. In: Proceedings of the IEEE International Test Conference, Washington D C, 1998. 284-293.
  • 7Varma P, Bhatia S. A structured test reuse methodology core-based system chips [A]. In: Proceedings of the IEEE International Test Conference, Washington D C, 1998. 294-302.
  • 8Chakrabarty K. Testing scheduling for core-based systems [A].In: Proceedings of International Conference on Computer-Aided Design, San Jose, California, 1999. 391-394.
  • 9Sugihara M, Date H, Yassuura H. A novel test methodology for core-based system LSIs and a testing time minimization problem[A]. In: Proceedings of the IEEE International Test Conference, Washington D C, 1998. 465-472.
  • 10Aerts J, Marinissen E J. Scan chain design for test time reduction in core-based Ics [A]. In: Proceedings of the IEEE International Test Conference, Washington D C, 1998. 448-457.

二级参考文献1

  • 1Petru Eles,Zebo Peng,Krzysztof Kuchcinski,Alexa Doboli. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search[J] 1997,Design Automation for Embedded Systems(1):5～32

共引文献11

同被引文献14

  • 1ITRS. Semiconductor industry association, international technology roadmap for semiconductors [ EB/OL ]. 2001. http://public. itrs. net/files/2001SIA Roadmap/ Home. htm.
  • 2MARINISSEN E J, GOEL S K, LOUSBERG M. Wrapper design for embedded core test [ C ]//Proc IEEE International Test Conference ( ITC ). Atlantic City: IEEE, 2000:911 -920.
  • 3IYENGAR V, CHAKABARTY K, MARINISSEN E J. Test wrapper and test access mechanism co-optimization for system-on-chip [ C ]// Proc IEEE International Test Conference (ITC). Baltimore:IEEE Press, 2001 : 1023 - 1032.
  • 4IYENGAR V, CHAKABARTY K, MARINISSEN E J. Test wrapper and test access mechanism co-optimization for system-on-chip [ J ]. Journal of Electronic Testing: Theory and Applications, 2002, 18 : 213 - 230.
  • 5IYENGAR V, CHAKABARTY K, MARINISSEN E J. Efficient test access mechanism optimization for systemon-chip [ J ]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003, 22 (5) : 635 -643.
  • 6IYENGAR V, CHAKABARTY K, MARINISSEN E J. Efficient wrapper/TAM co-optimization for large SoCs [ C]//Proc Design Automation and Test in Europe. Pairs:[ s. n. ] , 2002:491 -498.
  • 7GOEL S K, MARINISSEN E J. TAM architectures and their implication on test application time [ C ]//Proc IEEE International Workshop Testing Embedded CoreBased Systems (TECS). Marina del Ray: [ s. n. ], 2001 : 1 - 10.
  • 8IYENGAR V, CHAKRABARTY K, MARINISSEN E J. Test access mechanism optimization test scheduling and tester data volume reduction for system-on-chip [J]. IEEE Transactions on Computers, 2003 52(12) : 1619 - 1632.
  • 9KORANNE S. Design of reconfigurable access wrappers for embedded core based SoC test [ J ]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2003, 11 (5) : 955 - 960.
  • 10CHATrOPADHYAY S, REDDY K S. Genetic algorithm based test scheduling and test access mechanism design for system-on-chips [ C]//Proc. of the 16^th International Conference on VLSI Design (VLSI03) . Washington : IEEE Computer Society, 2003 : 341 - 346.

引证文献1

计算机辅助设计与图形学学报
2004年 第3期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部