摘要
提出了一种并行处理的编解码方案。采用这种方案 ,设计了万兆以太网 1 0 G BASE-R标准的物理编码子层发送端芯片。芯片由 64b/ 66b编码、扰码和变速箱 3部分组成。考虑到测试问题 ,该芯片内置了伪随机码数据源。这种方案的优点是逻辑简单、速度快。芯片采用 TSMC 0 .1 8μm CMOS工艺 ,用全定制方式实现。芯片引脚分布时参照 PLCC48规格。
A parallel coding-and-decoding method is presented, and a chip using 10 Gb Ethernet PCS transmitter based on 10 G BASE-R is designed. The chip is composed of 64 b/66 b encoding, scramble code and gearbox. Considering experimental conditions, a random data source is available in the chip. The method has the advantatges of simple structure and high speed. The chip is designed in full custom, using 0.18 μm CMOS technology. The pads are laid out referred to the package format of PLCC48.
出处
《数据采集与处理》
CSCD
2004年第1期95-98,共4页
Journal of Data Acquisition and Processing
基金
国家"8 63"计划 (2 0 0 1 AA1 2 1 0 74)资助项目
