低噪声、低功耗CMOS电荷泵锁相环设计

Design of Low-noise、Low-power Consumption CMOS CPPLL

设计了一种 1 .8V、0 .1 8μm工艺的低噪声低功耗锁相环电路 ,其采用 CSA(Current Steer Amplifier)架构的压控振荡器 (VCO)。整个电路功耗低 ,芯片面积为 1 60 μm× 1 2 0 μm,对电源和衬底噪声抑制能力强。经过Spice模拟表明 ,在有电源噪声的情况下 ,输出 5 0 0 MHz时钟时周对周抖动小于 41 ps,功耗为 2 .8m W。

In this paper, we present a 1.8 V、0.18 μm PLL. The proposed PLL is based on VCO with CSA (Current Steer Amplifier). This structure with chip area of 160μm×120 μm can provide low power consumption, high power supply noise and substrate noise rejection. According to the simulation results, the cycle-to-cycle jitter of the output clock at 500 MHz with supply noise is only 41ps. Its power dissipation is 2.8 mW. And the measurement results of IC agree with them.