一种适用于通用CPU的高命中率、低功耗TLB

An Architecture of a Low Miss-rate & Low Power TLB

为了提高 CPU的速度和更有效的管理物理内存 ,一般都采用转换查找缓冲器 (TLB)将虚拟地址转换为物理地址。文中介绍一种适用于 3 2位通用 CPU的 TLB结构。这种 TLB采用组相联映射、两种页粒度结构 ,采用静态存储结构作为其基本存储单元 ,同时应用了静态存储单元的低功耗设计来降低 TLB的功耗。

In order to optimize performance, including speed and the usage of its memory, CPU usually hires a Translation Lookaside Buffer(TLB) to translate the virtual address into physical address. This paper presents a structure of a TLB that can be rendered by a 32-bit general CPU. The architecture of the TLB has two-level and two-page sizes. The fundamental memory unit of the TLB is a static RAM. Moreover, a further design methodology that can reduce the power consumption of TLB is also presented.