DSP中MAC的微系统结构设计(英文)

The Micro-architecture Design for MAC in DSP

在实际的高性能定点数字信号处理器(DSP)设计过程中,往往需要设计一个功能复杂的乘累加器。也就是说,乘累加器不光是要同时完成通常所见的带符号数和无符号数的乘加及乘减运算,而且还需要同时完成整数乘加和小数乘加运算,无偏差的舍入运算,饱和等功能。另外,为了解决DSP中数据相关的问题,往往要求乘累加器在单拍完成所有的这些运算,因此很难找到一个高速度低成本的实现方案。文章首先给出了通常的高性能定点DSP中乘累加器所需要完成的功能需求,然后提出并实现了一个16位高性能乘累加器,将其所需要完成的上述各种功能巧妙地整合起来在单拍内完成,而完成所有上述功能只需要3级4押2压缩和一次超前进位的加法运算。该乘累加器采用0.35μm工艺实现,已经嵌入到数字信号处理器中并已经成功应用于实际的工程项目。

Usually we need to design a complex multiplier/accumulator (MAC) for a digital signal processor, and we have to implement many functions for the MAC in the DSP design. Not only we need to deal with the usual signed and unsigned numbers simultaneously, but solve the rounding, saturation, fraction and integer mode multiplication simultaneously. So it's difficult to find a high performance but low cost solution. This paper gives analysis for a general specification of the complicated multiply accumulation cell, and then presents a dedicated solution for a kind of complicated multiplier/accumulator. It's a high performance but low cost solution for MAC.