智能式自动逻辑综合系统KDLS

An Intelligent Automatic Logic Synthesis System KDLS

本文介绍一种智能式逻辑综合系统KDLS。它以寄存器传输语言(RTL)作为输入,采用基于知识的方法进行电路的结构设计、模块综合和电路的逻辑优化。对电路的延时优化问题也作了讨论。KDLS用C语言和人工智能语言ops5^+写成,迄今含有150多条规则。应用系统进行实例综合,取得了令人满意的结果。

This paper introduces an automatic logic synthesizing system KDLS. The input of the system is RTL (Register Transfer Language), and the knowledgebased method is used to implement the structure design, module synthesis and logic optimization. Timing optimization is also discussed. KDLS is written with C language and artificial intelligent language ops5^+ and now it has about 150 rules. The resuits obtained from KDLS are satisfactory.