新型数字下变频器的设计

New design of digital down-converter

提出了一种基于新型低比特位高阶Σ-Δ调制器用于数字下变频器(DDC)设计的新思路.该Σ-Δ调制器输出的比特位数比传统调制器要少得多,可以用它将高比特信号表示为低比特信号流,从而可在DDC的IF滤波器中用查表法替代乘法器,使得DDC的硬件实现更为简单,并且进一步提高了系统的工作频率.对DDC进行的仿真实验结果证明,这种DDC具有较高的工作频宽和抽取数等优良性能.

A digital down-converter (DDC) based on a lower-bit higher-order sigma-delta (Σ-Δ) modulator was proposed. The output of this Σ-Δ modulator has lower bits than that of the traditional Σ-Δ modulator and can be used to represent the higher-bits signal as a lower-bits one so that the lookup tables can replace the multipliers in the IF filter of the DDC to reduce the hardware cost and increase the system working frequency. The performance of this DDC was discussed. Simulation results show that this kind of DDC has satisfying performance such as wider working frequency bandwidth and higher factor of downsampling.