板级SRAM的内建自测试(BIST)设计

BIST for SRAM in PCB Level

板级SRAM的内建自测试的设计,是为了确保板级SRAM的可靠性。考虑到板级SRAM各种故障模型,选择使用MarchC-SOF算法,其对呆滞故障、跳变故障、开路故障、地址译码器故障和字节间组合故障有100%的故障覆盖率,优化面向"字节"的MarchC-SOF算法和扩展延时元素后,算法可对SRAM进行字节内组合故障和数据维持力故障测试。同时在只增加少量成本的情况下,使用FPGA构成存储器的BIST控制器,可以满足SRAM的可测性的要求。

SRAM is widely used in digital system.In order to maintain its reliability,a BIST structure in PCB level is presented.The fault models in SRAM are discussed first,and then March C-SOF algorithm is selected in the design.It has 100% fault coverage for SAFs,SOFs,TFs,AFs and inter-CFs.Optimized the word-oriented March C-SOF algorithm and added Del element,the algorithm can be used to deal with the intra-CFs and DRFs.A BIST controller,which is realized by using a FPGA,is presented in the last sector of the paper.The test system meets the need for testability in the condition of little additional cost.