千兆以太网物理层时钟产生/倍频单片集成电路设计

Monolithic integrated clock generator/multiplier for gigabit Ethernet

给出了一个基于TSMC 0 1 8μmCMOS工艺设计的千兆以太网物理层时钟产生 /倍频单片集成电路 .芯片采用电荷泵结构的锁相环实现 ,包括环形压控振荡器、分频器、鉴频鉴相器、电荷泵和环路滤波器等模块 ,总面积为 1 1mm× 0 8mm .采用 1 8V单电源供电 ,测得在负载为 5 0Ω时电路的输出功率大于 5dBm .芯片在PCB板上键合实现锁相环路的闭环测试 ,测得锁定范围为1 30MHz;当环路锁定在 1GHz时 ,振荡器输出信号的占空比为 5 0 4% ,rms抖动为 5 4ps,单边带相位噪声为 - 1 2 4dBc/Hz @1 0MHz .该电路适当调整可应用于千兆以太网IEEE80 2 3规范1 0 0 0BASE X的物理层发信机设计 .

A monolithic integrated clock generator/multiplier using TSMC 0.18 (μm CMOS technology for gigabit Ethernet has been realized and characterized. Based on charge pump phase locked loop (PLL) structure, the circuit consists of a voltage controlled oscillator (VCO), a divider, a phase/ frequency detector, a charge pump, a loop filter, etc. The total chip size is 1.1 mm × 0.8 mm. At a supply voltage of 1.8 V, the measured output power is more than 5 dBm based on 50 Ω load. The loop was closed through bonding. The measured locking range is approximately 130 MHz. At the locked frequency of 1 GHz the phase noise, duty cycle and rms jitter are measured to be -124 dBc/Hz@10MHz, 50.4% and 5.4ps, respectively. This circuit can be adopted in the IEEE802.3 type 1000BASE-X transmitter after appropriate modification.