流水线技术在FPGA设计中的应用

Application of Pipeline Technology in FPGA Design

本文讨论了在FPGA中设计流水线加法器、乘法器和 1 6阶低通滤波器的设计方法 ,并以一个 1 6阶低通FIR滤波器设计为例 ,对该方法设计的加法器、乘法器和滤波器进行性能对比 。

This paper discusses the methods of the design of the pipeline adder and multiplicator and the 16-step low pass FIR filter in FPGA.Taking the design of the 16-step low-pass FIR filter as an example, the authors make a comparison among the performances of the adder, multiplicator and filter, the work proves that the pipeline method improves the calculating speed satisfactorily.