一种低功耗的高性能四路组相联CMOS高速缓冲存储器(英文)

A Low-Power Super-Performance Four-Way Set-Associative CMOS Cache Memory

采用 0 .1 8μm/ 1 .8V1 P6 M数字 CMOS工艺设计并实现了一种用于高性能 32位 RISC微处理器的 6 4 kb四路组相联片上高速缓冲存储器 (cache) .当采用串行访问方式时 ,该四路组相联 cache的功耗比采用传统并行访问方式在 cache命中时降低 2 6 % ,在 cache失效时降低 35 % .该 cache的设计中还采用了高速电路模块如高速电流灵敏放大器和分裂式动态 tag比较器等来提高电路工作速度 .电路仿真结果显示 cache命中时从时钟输入到数据输出的延时为 2 .

A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...