数据缓冲器的低功耗设计

Low Power Design of a Data Buffer

首先介绍“九五”期间研制的LSMPP协处理器的数据缓冲器的功能与设计 ,并从降低活动因子的角度提出了一种针对低功耗的改进 ,如果阵列的大小为N×N ,则功耗可以降低到“九五”期间方案的 1/N 然后又提出一种针对引出头的减少的改进方法 ,引出头的减少是与互连方案有关的 ,一路串行互连方案可以减少 4N个 ,两路并行互连方案可以减少 8N个 最后提出了一种新的数据缓冲器的设计方案 ,每一时刻只有一个PE的数据缓冲器是传送数据的 ,功耗降低为“九五”期间方案的 1/ (N×N) 。

The design and function of a data buffer of LS MPP co processor designed in 'Ninth Five Year Plan' is introduced first Then a novel method to reduce its power dissipation and its I/O pads is put forward Finally a new scheme of the data buffer is proposed It can be assured that only one PE's data buffer is active when the PE array exchanges data with the external memory As a result, the power dissipation is reduced to one N×Nth, and is dependent of the scales of PE array