基于FPGA的多约束长度Viterbi译码器

Research into the multi-constraint lengths Viterbi decode

现有的各通信系统中卷积码的约束长度各不相同.为充分利用现有资源很有必要研究多约束长度的Viterbi译码器.基于FPGA讨论了实现多约束长度的卷积码的Viterbi译码器的一些问题.主要讨论了分支度量单元(BMU)、加比选单元(ACS)、路径度量寄存器单元(PMU)和幸存路径存储器单元(SVU)实现中的一些问题.

Existent communication specifies a different configuration for the convolutional coding. This motivates the need for a Viterbi decoder which has the capability to dynamically switch stands. The design of different constraint lengths and code rate Viterbi decoder were stadied, including BMU, ACS, PMU and SVU.