低功耗双边沿触发计数器的设计

Design of Low Power Double Edge Triggered Counter

该文从消除时钟信号冗余跳变而致的无效功耗的要求出发,提出了应用并行技术和流水线技术,实现基于RTL级的双边沿触发计数器的设计。经EDA软件模拟仿真和FPGA硬件验证,表明该计数器具有正确的逻辑功能,能够正常地应用于数字系统的设计。由于时钟工作频率减半及所需工作电压的降低,可使系统功耗明显减少。

To erase the bootless power dissipation of the redundant leap of the clock,this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.It is proved that this type of counter has correct logic function according to EDA simulation and experimental verification with FPGA and can be normally used in the design of digital system.By using the half working frequency of the clock and reducing the voltage of the circuits,power dissipation of the system can be reduced evidently.