一种高性能、低功耗乘法器的设计

Design of low power and high speed multiplier

基于标准单元方法设计并实现支持单指令流多数据流(SIMD)计算的16bit×8bit乘法器.分析乘法运算时延的分布,采用Wallace树形结构实现Booth乘法器,最终进位传递计算采用从左到右免除进位(LRCF)算法,使最高位(MSB)部分的进位传递计算与部分积相加运算的并行重叠进行,以提高乘法运算的并行度,降低硬件复杂度和功耗.在0.18μm工艺标准单元库的支持下,使用电子设计辅助(EDA)工具,版图实现了该乘法器.利用版图得到的线负载模型信息对门级网表进行分析,在工作电压为1.62V,125℃时,该乘法器速度为2.80ns,功耗为0.089mW/MHz.

The structure of a low-power 16 bit by 8 bit two's complement multiplier unit in the design of a DSP (digital signal processor) chip was proposed based on standard cell. The multiplier used modified Booth's algorithm to generate the partial products, a Wallace tree structure to achieve the high-speed partial products addition, and finally, a high speed carry lookahead adder to finish the carry propagation. The delay of the carry propagation plays a very important role in the whole delay of the multiplier. To solve this problem, the LRCF (left-to-right-carry-free) algorithm was applied to complete the MSB (most significant bits) result calculation partially parallel with the Wallace tree addition. The power consumption distribution within this multiplier was analyzed and some methods were applied to reduce the switching activity of the Wallace tree structure to reduce the power consumption. Based on the UMC 0.18 μm CMOS technology standard cell library, the reports of Design Power showed that the multiplier can achieve the speed of 2.80 ns, an average dynamic power dissipation of 0.089 mW/MHz at 1.62 V and 125°C.