±50 Mvar链式STATCOM脉冲发生器设计

PULSE GENERATOR FOR ±50 MVAR CASCADE STATCOM

介绍了用于±50 Mvar链式静止无功发生器(STATCOM)的基频优化脉宽调制(PWM)的脉冲发生器。根据链式逆变器电路结构的特点制定了基频优化PWM方案。脉冲发生器采用数字信号处理器(DSP)加现场可编程逻辑门阵列(FPGA)作为主要的处理器,根据两者各自的特点分配功能,提高了脉冲发生器的总体性能。该脉冲发生器在20 kVA链式STATCOM原理样机中可靠运行,实验结果证明了设计的正确性。

This paper presents the design of a pulse generator to implement an optimal pulse width modulation for ±50 Mvar cascade STATCOM. The basic principles of the fundamental frequency optimal PWM are analyzed, based on which a pulse generator is designed. The pulse generator uses digital signal processor (DSP) and field programmable gate array (FPGA) as kernel processors, which combines fast floating calculation ability of DSP and super Boolean calculation ability of FPGA so as to achieve a good performance. The main principles, implementation method and hardware configuration of the generator are described. The pulse generator has been applied to a 20 kVA b prototype and the experimental results confirm validity of the pulse generator.