用FPGA实现曼彻斯特编解码

The Implementation of Manchester Encoder andDecoder Utilizing FPGA

使用MAXPLUSⅡ和FPGACompilerⅡ软件及VHDL硬件描述语言 ,采用自顶向下设计方法设计曼彻斯特编解码器 ,每帧数据包括同步字、有效数据和冗余校验位三部分 ,最终在Altera公司的FPGA芯片EPF1 0K1 0LC84 4进行验证 .实验结果表明 ,FPGA能很好地实现曼彻斯特编解码器 ,而且该编解码方式具有抗干扰能力强 。

A Manchester Coder Decoder is designed using the software MAXPLUSⅡ, FPGACompiler Ⅱ and the hardware descriptive language VHDL in line with the top down method, to be implemented in an EPF10K10LC84 4 chip of PFGA type manufactured by Altera Co..Decoding process included synchronous head,data bits determination and CRC checking.The experiment results have proved that FPGA can implement Manchester Coding Decoding and this kind of Coding Decoding method has many advantages such as strong anti interference ability and the high data transmission rate,etc.