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亚0.1μm栅长CMOS器件和电路的研制 被引量:1

Development of CMOS Devices and Circuits with Sub-0.1μm Gate Length
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摘要 利用侧墙图形转移实现亚 0 .1μm栅线条 ,重掺杂多晶硅做固相扩散源实现 CMOS晶体管超浅源漏扩展区 ,并且将二者有机结合起来 ,成功实现了栅长约为 84 .6 nm的 CMOS器件和电路 .报道了利用重掺杂多晶硅固相扩散同时实现 CMOS源漏扩展区的方法 . A newly developed method of pattern shift with spacer is proposed to define sub 0 1μm MOS transistor gates.Polysilicon doped heavily is introduced as solid phase diffusion source to realize ultra shallow source and drain extensions.Using the process of integration of these two methods,which is basically compatible with standard process,the nanoscale devices and circuits with gate length of 84 6nm are fabricated with relatively good performance.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2004年第5期583-588,共6页 半导体学报(英文版)
基金 国家重点基础研究发展规划 (批准号 :G2 0 0 0 0 3 65 0 1) 国家自然科学基金(批准号 :90 2 0 70 0 4)资助项目~~
关键词 侧墙图形转移技术 固相扩散 源漏扩展区 spacer pattern shift technology solid phase diffusion source and drain extension
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参考文献25

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同被引文献19

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