射频同步高阶环的设计

High-Order Phase-Locked Loop Design for Radio Frequency Synchronization

文章介绍一种用于射频同步的高阶环设计方法。主要围绕高阶环参数设置与环路稳定性的关系进行了分析,导出了满足稳定性条件的环路参数,同时给出了环路滤波器的数字实现框图,并对整个环路的参数设置进行了计算机仿真验证。

A high-order phase-locked loop(PLL) for radio frequency synchronization is designed. The relationship between stability and parameters design of the LF1 is analyzed, and so the parameters which satisfy the stability demands can be obtained. A digital circuit to realize the LF1 is put out, and computer simulations are taken to testify the parameters design of the PLL.