采样-保持电路中的一种增益误差自校正方法

A Kind of Gain Error Correction Scheme for Sample-and-Hold Circuits

提出一种用于流水线模数转换器(ADC)中的模拟增益误差自校正电路.该电路由一个可编程电容阵列、一个比较器和一小块数字电路组成,通过对第一级采样-保持电路的增益进行校正,使它的增益误差达到12bit转换精度的要求.仿真结果表明,整个流水线ADC的有效量化位数从原来的9.95bit提高到11bit.

A simple scheme for correcting the gain error of sample-and-hold circuits (S/H) using analog technique was proposed. This scheme consists of a programmable capacitor array, a comparator and a small amount of low speed digital circuits. The resultant unit gain of S/H of the first stage can reach an accuracy better than 12 bits with typical amplifier and comparator offset voltages being allowed for. The simulation results indicate that the ENOB of A/D converter reaches 11 bit with trimming on.