异步时序逻辑电路设计的一种简明方法

Simple Method to Design Asynchronous Sequential Logic Circuit

提出了一种异步时序电路设计的新方法:时钟信号与次态卡诺图联立法.根据时钟信号填写次态卡诺图,当触发器满足时钟信号时其次态由状态转换图决定,否则其次态为约束项.据此可方便求出驱动方程并判断自启动.

This paper presents a new method to design asynchronous sequential circuit:clock signals and secondary state Karnaugy Map uniting method.A secondary Karnaugh Map is filled in based on clock signals,when the filp-flop satisfies the clock signals ,its state follows the state-shift map.If not ,the latter is a restrictive item.On these grounds ,drive equation can be easily deduced .Then we can judge whether the circuit can start automatically.