摘要
采用一种适合于硬件实现的流水线伪中值滤波算法,利用FIFO器件和FPGA器件,完成8bit图像3×3窗口的列方式伪中值滤波,整个电路去噪效果明显.
A pipeline- pseudo median filtering algorithm is suitable to hardware realizing,and is utilized. The 8 bit image 3 × 3 window median filter is implemented by using FPGA devices and FIFO devices. The significant result of noise suppression is achieved.
出处
《河海大学常州分校学报》
2004年第2期44-46,共3页
Journal of Hohai University Changzhou