10Gbit/s0.18μmCMOS1∶4分接集成电路

IC design of 10 Gbit/s 0.18 μm CMOS 1∶4 DEMUX

研究了万兆以太网接收芯片结构 ,并在此基础上设计、流片和测试了高速 1∶4分接芯片 ,采用 0 .1 8μmCMOS工艺设计的1∶4分接电路 ,实现了满足 1 0GBASE R的 1 0 .31 2 5Gbit/s数据的 1∶4串 /并转换 ,芯片面积 1 1 0 0 μm× 80 0 μm ,在输入单端摆幅为 80 0mV ,输出负载 5 0Ω条件下 ,输出2 .5 78Gbit/s数据信号电压峰峰值为 2 2 8mV ,抖动为 4psRMS ,眼图的占空比为 5 5 .9% ,上升沿时间为 5 8ps .在电源为 1 .8V时 ,功耗为 5 0 0mW .电路最高可实现 1 3.5Gbit/s的

Based on the research of 10 Gigabit Ethernet demultiplexer structure, a high s peed 1∶4 demuxplexer (DEMUX) was designed, fabricated and test ed. The DEMUX chips produced in 0.18 μm CMOS process have a function of 1∶4 demultiplexing and can operate at 10.312 5 Gbit/s satisfying 10GBASE R. Its area is 1 100 μm×800 μm. Under the condition of 800 mV input swing and 50 Ω output load,the peak to peak voltage of 2.578 Gbit/s output signal is 228 mV, the rising time is 58 ps, and the root mean square (RMS) jitter is 4 ps. The power consumption is 500 mW under 1.8 V supply voltage. The highest operating data rate tested is 13.5 Gbit/s.