基于VHDL语言的数字锁相环的设计与实现

Design of Digital Phase Locked Loop Based on VHDL

为了改善数字通信系统的同步性能,保证系统工作稳定、可靠,对锁相环电路进行了研究。在分析模拟锁相环缺点的基础上,介绍了数字锁相环的工作原理,并用VHDL语言对该系统进行了设计,给出了数字锁相环电路3个主要模块的设计过程及仿真结果,得到了该系统的顶层电路。实验及仿真结果表明,数字锁相环是解决同步问题的重要措施之一。

The principle of the Digital Phase Locked Loop has been discussed in order to improve the synchronization of the digital communication system and to make the system stable and reliable. Based on the analysis of the fault of the analog phase locked loop, the theory of the digital PLL has been introduced, and the system is designed using VHDL. The designing procedure and the simulating results of the three main modules in the digital PLL circuit are given. At the same time, a top level circuit of the system is got. The results of lab and simulation of the system show that the digital PLL is one of the important methods to solve the synchronization problem.